IBM promises 19% reduction on 65nm CELL
So, aside from reducing die size and manufacturing costs, the next inherent effect for IBM‘s CELL BE processor to take the hike down the 65nm road is lower power consumption. While lower power consumption could also mean lower power waste (heat generation), we decided not to put on the geek hat just yet.
Since Intel and AMD have already travelled that road and with rumors that Intel is designing a test prototype of an 80-core 40nm processor, you can say that IBM has been taking its sweet time with adopting the 65nm version, even after Sony had announced their 65nm CELL production for the PlayStation 3.
What were they so afraid of? Well, to step up expectations for this 6 GHz CMOS SOI processor, they had to analyze the effects of reducing voltage requirements on the die, including the need for dual voltage railings. Yes, two voltage railings, targeted at a planned 1.3V level per rail.
The voltage of the power supplying the new CELL BE has been stepped up by 200mV to keep the 65nm puppy stable and happy. The increase in voltage results to a prevention of “scatter” and “leakage,” thereby reducing actual power consumption by approximately 19%.
Yes, that’s all well and good, but what effect does this have to do with price? IBM isn’t keen to answer that, but geeks know the answer to that question.
Via BetaNews
So, aside from reducing die size and manufacturing costs, the next inherent effect for IBM‘s CELL BE processor to take the hike down the 65nm road is lower power consumption. While lower power consumption could also mean lower power waste (heat generation), we decided not to put on the geek hat just yet.
Since Intel and AMD have already travelled that road and with rumors that Intel is designing a test prototype of an 80-core 40nm processor, you can say that IBM has been taking its sweet time with adopting the 65nm version, even after Sony had announced their 65nm CELL production for the PlayStation 3.
What were they so afraid of? Well, to step up expectations for this 6 GHz CMOS SOI processor, they had to analyze the effects of reducing voltage requirements on the die, including the need for dual voltage railings. Yes, two voltage railings, targeted at a planned 1.3V level per rail.
The voltage of the power supplying the new CELL BE has been stepped up by 200mV to keep the 65nm puppy stable and happy. The increase in voltage results to a prevention of “scatter” and “leakage,” thereby reducing actual power consumption by approximately 19%.
Yes, that’s all well and good, but what effect does this have to do with price? IBM isn’t keen to answer that, but geeks know the answer to that question.
Via BetaNews
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